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RISC-V support in MSIM
Thesis title in Czech: Podpora RISC-V v MSIMu
Thesis title in English: RISC-V support in MSIM
Key words: RISC-V|MSIM|simulátor|instrukční sada
English key words: RISC-V|MSIM|simulator|instruction set
Academic year of topic announcement: 2022/2023
Thesis type: Bachelor's thesis
Thesis language: angličtina
Department: Department of Distributed and Dependable Systems (32-KDSS)
Supervisor: Mgr. Vojtěch Horký, Ph.D.
Author: hidden - assigned and confirmed by the Study Dept.
Date of registration: 10.10.2022
Date of assignment: 10.10.2022
Confirmed by Study dept. on: 17.10.2022
Date and time of defence: 07.02.2023 09:00
Date of electronic submission:02.01.2023
Date of submission of printed version:02.01.2023
Date of proceeded defence: 07.02.2023
Opponents: Mgr. Filip Kliber
The goal of this thesis is to implement support for RISC-V processor in the MSIM machine emulator.

At the moment, MSIM supports only MIPS R4000 CPU as its execution unit. The implementation will add support for a new type of CPU with the RISC-V architecture.

The extension will follow current concepts of MSIM where focus is on ease of debugging and reproducibility at the expense of performance. As a proof of concept, the author will also provide a simple bootstrap code that can switch to execution of a compiled C code with a computational task and output the result to the existing console-style device in MSIM.

The text of the thesis will focus on the analysis of the required and optional features of the selected architecture and on achieving reasonable support allowing possible replacement of MIPS with RISC-V as the selected architecture for the Operating systems course.

Tentative list of reviewers: Petr Tůma, Martin Kruliš, Jakub Yaghob
RISC-V specifications, available on-line at

MSIM documentation, available on-line at
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